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| Analog/Digital Mixed ASIC MIXED SIGNAL ASIC MA-8A, MA-9 Family June 2003 CONTENTS Mixed Signal Applications ************************ 3 Mixed Signal ASIC Product Lines ************ 5 MA-8A ************************************************** 8 MA-9 Family *************************************** 21 Packages ******************************************* 36 NEC Electronics' mixed signal solutions Taking on New Challenges Toward the Next Generation Pamphlet A13326EJ2V0PF Mixed Signal Applications Mixed signal ASICs enable higher quality and a better cost performance in AFE (analog front end) circuits and battery management circuits for applications such as sensors, PC peripheral equipment, and mobile devices. Sensors Peripheral equipment Mobile devices Sensor signal control Pick-up control Servo control Light intensity detection Auto-focus Flash light control Battery power control Pamphlet A13326EJ2V0PF 3 Application Concept Applications dealing with "minute analog signal input in a wide band" require signal amplifiers or analog-digital arithmetic circuits (analog front end: AFE) for the analog interface. Also, for mobile equipment, the need to extend the battery life means an improved power efficiency is essential. NEC Electronics provides a custom-built battery management IC for cellular phones and other mobile applications. AFE (Analog Front End) Analog I/F, analog signal processing Analog signal Analog circuit (amplification) Sensor 1 A/D converter CPU, Cell-based IC Digital circuit (logic) Sensor 2 Sensor 3 D/A converter Accessory drive Voltage regulator Battery charger Power MOS FET Battery Vibrator, LED, etc. Battery management Power on/off control Efficient battery control 4 Pamphlet A13326EJ2V0PF Mixed Signal ASIC Product Lines NEC Electronics offers mixed signal ASICs that employ a BiCMOS process with a process rule of 0.65 m to 0.35 m. Furthermore, the 0.35 m BiCMOS can incorporate our 0.35 m cell-based IC CB-9 Family VX Type analog core. MA-8A ( PD688xx) 0.65 m BiCMOS process 5 V power supply (supports 3.3 V library) Logic circuit (Gate array configuration) Analog circuit (Fully customized configuration) MA-9 Family ( PD681xx) 0.35 m BiCMOS process (Equivalent to CB-9VX) 3.3 V power supply For large-scale systems Logic circuit (Cell-based configuration) Cell-based IP core Analog circuit (Fully customized configuration) Pamphlet A13326EJ2V0PF 5 Mixed Signal ASIC Product Lines Integration, function Analog masters PC5204 PC5704 PC5022 PC5021 PC5020 PC5023 PC5734 PC5032 PC5031 PC5203 PC5202 PC5201 PC5200 Mixed signal ASIC PC5703 PC5702 PC5701 A/D, D/A IP coreNote Analog circuit (Fully customized) Logic circuit (Equivalent to CB-9VX) Analog circuit (Fully customized) Logic circuit Analog Digital MA-9 Family Integration 0.35 m BiCMOS process MA-8A 0.65 m BiCMOS process Note A CB-9VX macro can be mounted but not a ROM or CPU. 3.3 5 9 12 42 Voltage(V) 6 Pamphlet A13326EJ2V0PF Support of Small-Scale Packages In addition to conventional mold packages, various CSPs (chip size packages) are available to support set downsizing. FPBGATM (Fine-pitch BGA) FPLGA (Fine-pitch LGA) Pamphlet A13326EJ2V0PF 7 0.65 m Mixed Signal ASIC MA-8A Features Support of digital/analog mixed circuits By employing the latest BiCMOS process, the MA-8A realizes the integration of a 0.65 m CMOS gate array and analog ASIC (analog master) on a single chip. Analog block element configuration prioritizing circuit functions Analog circuits that mix bipolar transistors and CMOS transistors can be created through the use of the BiCMOS process: High input impedance operational amplifiers Sample and hold circuits Analog switches, etc. Simple design and short development time The logic block can be easily developed with OPENCADTM (NEC Electronics' original CAE tool). Furthermore, a short development time can be achieved, which is another advantage of ASICs. 8 Pamphlet A13326EJ2V0PF MA-8A Application Fields The MA-8A can be used to integrate analog/digital mixed circuits applied to multimedia and various other fields on one chip. Mobile devices (battery management/speaker drive) Cellular phones (PDC, PHS, CDMA, GSM, GPRS) PDAs Portable game equipment PC peripheral equipment DSCs, single-lens reflex cameras Flash light control, zoom lens control Storage equipment Servo controller LCD panels (active matrix) Grayscale power supply controller Sensor modules Geomagnetic sensors (cellular phone GPS, etc.) Gyro sensors (compensating for hand-shake in DSC, DVC) Magnetic sensors (DC motor control, etc.) Pamphlet A13326EJ2V0PF 9 MA-8A MA-8A Application Examples Cellular Phones (Battery Management) RF interface Base band, CPU Microphone Speaker Accessory drive SW LDO voltage regulator LDO voltage regulator LDO voltage regulator Li-ion battery charger Power MOS FET Li-ion battery Vibrator, LED, etc. 10 Pamphlet A13326EJ2V0PF MA-8A Digital Still Cameras, Single Lens Reflex Cameras (Zoom Lens Control) Impedance conversion Amplification Comparison Logic circuit DC motor Oscillator Crystal resonator As many as there are motors Reference voltage adjustment Temperature and other detectors DC motor encoder circuit Pamphlet A13326EJ2V0PF 11 MA-8A Chip Configuration The MA-8A is mainly composed of a logic circuit (gate array block) and an analog circuit. The I/O cells for the digital/analog interface perform input/output of digital signals between the logic circuit and the analog circuit. Digital circuit pad I/O cell Logic circuit internal cell area I/O cell for digital/analog interface Internal cell Analog circuit Analog circuit pad I/O Cells for Digital/Analog Interface Analog circuit test switching pin Test pins Logic circuit test switching pin Logic circuit internal cell area Analog circuit internal cell area I/O cell for digital/ analog interface 12 Digital signals Pamphlet A13326EJ2V0PF MA-8A Basic Specifications Logic Circuit PD688 0.65 m BiCMOS process 5.0 V 0.5 V (I/O block, internal gates) CMOS, TTL Internal gatesNote 1 Delay time Input bufferNote 2 Output bufferNote 3 190 ps (TYP.) 340 ps (TYP.) 2.13 ns (TYP.) Part number Process Supply voltage Interface level Notes 1. Value assuming 2-input NAND power gate, fan-out 1, and wiring length 0.6 mm/1 pin pair. 2. Value assuming fan-out 2, wiring length 0.6 mm/1 pin pair. 3. Value assuming load capacitance 15 pF, block name FO01. Remark The logic circuit characteristics are the same as those of NEC Electronics' CMOS-8 Family. Analog Circuit Part number Process Supply voltage NPN type Transistors PNP type (lateral) MOS Polysilicon resistorNote Capacitor (MOS type)Note PD688 0.65 m BiCMOS process 5.0 V 0.5 V fT = 10 GHz, hFE = 80 (all TYP.) fT = 10 MHz, hFE = 70 (all TYP.) N-ch type, P-ch type for analog circuit Absolute precision: 20%, relative precision: 2% (all MAX.) Absolute precision: 15%, relative precision: 2% (all MAX.) Note Values indicated are for reference only. The relative precision applies only to when the element is positioned in an adjacent location. Pamphlet A13326EJ2V0PF 13 MA-8A Electrical Specifications Absolute Maximum Ratings Item Supply voltage Input/output voltage (logic circuit) Input current (logic circuit) Output current (logic circuit) Symbol VDD,VCC VI / VO II IO IOL = 3 mA IOL = 6 mA IOL = 9 mA IOL = 12 mA IOL = 18 mA IOL = 24 mA Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.5 to +6.0 -0.5 to VDD + 0.5 20 10 15 20 30 40 60 -40 to +85 -65 to +150 Unit V V mA mA mA mA mA mA mA C C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Definition of absolute maximum rating terms Item Supply voltage Input voltage Output voltage Input current Output current Symbol VDD VI VO II IO Meaning The range of voltage that, if applied to the VDD pin, will not cause destruction or lower reliability. The range of voltage that, if applied to the input pin, will not cause destruction or lower reliability. The range of voltage that, if applied to the output pin, will not cause destruction or lower reliability. The absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur. The absolute value of DC current capacity that, if output from or input to the output pin, will not cause destruction or lower reliability. Range of ambient temperature in which normal logical operation will occur. Range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied. Operating ambient TA temperature Storage Tstg temperature 14 Pamphlet A13326EJ2V0PF MA-8A Recommended Operating Range (Logic Circuit) Standard specification CMOS interface conditions VDD = 5 V 10%, TA = -40 to +85C (TJ = -40 to +125C) Item Supply voltage High-level input voltage Low-level input voltage Positive trigger voltage Negative trigger voltage Hysteresis voltage High-level input voltage Low-level input voltage Positive trigger voltage Negative trigger voltage Hysteresis voltage Input rise time Input fall time Input rise time Input fall time Note Do not use this for the clock signal. Remark If a signal with a long rise/fall time is input, use a Schmitt trigger input buffer to prevent malfunction due to noise superimposed on the signal line. Fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the Schmitt trigger input buffer, and therefore, care must be exercised in laying out the pins. Symbol VDD VIH VIL VP VN VH VIH VIL VP VN VH tri Normal input tfi tri Schmitt inputNote tfi 0 10 ms 0 0 200 10 ns ms TTL interface CMOS interface Conditions MIN 4.5 0.7VDD 0 1.80 0.60 0.30 2.29 0 1.15 0.59 0.27 0 TYP 5.0 MAX 5.5 VDD 0.3VDD 4.00 3.10 1.50 VDD 0.77 2.54 1.85 1.50 200 Unit V V V V V V V V V V V ns Pamphlet A13326EJ2V0PF 15 MA-8A Standard specification TTL interface conditions VDD = 5 V 10%, TA = 0 to +70C (TJ = 0 to +100C) Item Supply voltage High-level input voltage Low-level input voltage Positive trigger voltage Negative trigger voltage Hysteresis voltage High-level input voltage Low-level input voltage Positive trigger voltage Negative trigger voltage Hysteresis voltage Input rise time Input fall time Input rise time Input fall time Note Do not use this for the clock signal. Remark If a signal with a long rise/fall time is input, use a Schmitt trigger input buffer to prevent malfunction due to noise superimposed on the signal line. Fluctuation of power caused by simultaneous operation of output buffers lowers the capability of the Schmitt trigger input buffer, and therefore, care must be exercised in laying out the pins. Symbol VDD VIH VIL VP VN VH VIH VIL VP VN VH tri Normal input tfi tri Schmitt inputNote tfi 0 10 ms 0 0 200 10 ns ms TTL interface CMOS interface Conditions MIN 4.5 0.7VDD 0.0 1.90 0.63 0.31 2.20 0.0 1.20 0.60 0.30 0 TYP 5.0 MAX 5.5 VDD 0.3VDD 4.00 3.10 1.50 VDD 0.8 2.40 1.80 1.50 200 Unit V V V V V V V V V V V ns 16 Pamphlet A13326EJ2V0PF MA-8A MA-8A Development Procedure Development of the MA-8A is carried out by both the user and NEC Electronics by dividing the work between gate array design using the design resources of the user and circuit design applying NEC Electronics' analog ASIC technology, which results in a shorter development time. The transition of development work between the user and NEC Electronics is called "interfacing." The interface level depends on how far the user carries out development work and what data the user provides to NEC Electronics. Circuit diagram level interface In this development method, the user takes care of system circuit design, and the subsequent LSI circuit design and simulation are performed by NEC Electronics. Simulation level interface In this development method, the user is in charge of development from circuit design to simulation using engineering workstations (EWS) and CAD system simulation tools, and NEC Electronics is responsible for the rest of the development work. The MA-8A is divided into a logic circuit and an analog circuit, and two kinds of development methods combining the above-described interface levels are available. Development Method 1 [Logic circuit] Simulation level interface System Circuit Design LSI Circuit Design Circuit Synthesis Layout Design ES Production (User side) (NEC Electronics side) [Analog circuit] Circuit diagram level interface 2 [Logic circuit] Circuit diagram level interface [Analog circuit] Circuit diagram level interface Pamphlet A13326EJ2V0PF 17 MA-8A 1 Logic circuit: Simulation level interface Analog circuit: Circuit diagram level interface NEC Electronics Development support User Determination of desired system specifications System circuit design Analog circuit interface Circuit specification adjustment Analog circuit: Circuit design, simulation Simulation result verification Confirmation of provisional specifications Confirmation I/O buffer block design for digital/analog interface Logic circuit: Logic design and circuit design Circuit connection synthesis Simulation and creation of test pattern Analog circuit: Placement and routing Logic circuit: Placement and routing Mask production, ES production ES evaluation Confirmation Preparation of product specifications Verification of product specifications Confirmation CS production CS evaluation MP production Delivery 18 Pamphlet A13326EJ2V0PF MA-8A 2 Logic circuit: Circuit diagram level interface Analog circuit: Circuit diagram level interface NEC Electronics Development support User Determination of desired system specifications System circuit design Analog circuit interface Circuit specification adjustment Simulation result verification Confirmation of provisional specifications Confirmation Analog circuit: Circuit design, simulation Design of I/O buffer block for digital/analog interface Simulation Creation of test pattern Logic circuit: Logic design and circuit design Circuit connection synthesis Analog circuit: Placement and routing Logic circuit: Placement and routing Mask production, ES production ES evaluation Confirmation Preparation of product specifications Verification of product specifications Confirmation CS production CS evaluation MP production Delivery Pamphlet A13326EJ2V0PF 19 MA-8A MA-8A Development Tools The MA-8A provides development tools that support ASIC development by the user for the logic circuits. NEC Electronics will take charge of circuit design for the analog circuits according to the user's specifications. Caution A pin should be drawn out as a test pin where the analog circuit is connected to the logic circuit. Configure the area where the analog circuit is connected to the logic circuit, as well as the test circuit of the logic circuit in the test circuit block. Logic circuit (Gate array block) (Test circuit block) Designed by user or NEC Electronics OPENCAD (NEC Electronics' original CAE tool) Analog circuit Designed by NEC Electronics 20 Pamphlet A13326EJ2V0PF 0.35 m Mixed Signal ASIC MA-9 Family Features The MA-9 Family ( PD681) consists of mixed signal ASICs that aim for system-ona-chip through the use of a leading-edge 0.35 BiCMOS process pioneered by NEC m Electronics. Support of analog IP core The MA-9 Family can utilize analog circuit design resources such as the A/D converter and D/A converter of NEC Electronics' 0.35 cell-based IC. m Leading-edge BiCMOS process High-speed digital circuits and high-accuracy, sophisticated analog circuits can now be realized on a single chip by employing NEC Electronics' leading-edge 0.35 BiCMOS m process. Low power consumption A low power consumption is achieved for LSIs by employing a low-voltage operation process (3.3 V). Flexible mixed signal development environment NEC Electronics' development environment for the CB-9 Family VX Type cell-based IC can be used for the internal logic. Pamphlet A13326EJ2V0PF 21 MA-9 Family Application Fields Since CB-9 and later submicron cell-based ICs cannot configure an analog circuit, they may not support CB solutions. Furthermore, if they incorporate an A/D converter and D/A converter, a good cost performance is not possible due to the restrictions on cell-based IC allocation. In these cases, by integrating the entire cell-based IC, or the A/D converter, D/A converter, and analog circuit blocks on a single chip, the MA-9 Family provides the user with the best solution. Storage equipment Servo/write control DVD-ROM/RAM drives CD-R/W drives PC peripheral terminals Analog front end (A/D converter, D/A converter, analog circuit) Sensor signal amplification Color LCD panels Printers PDAs Sensor modules Geomagnetic sensors (cellular phone GPS, etc.) Gyro sensors (compensating for hand-shake in DSC, DVC) Magnetic sensors (DC motor control, etc.) 22 Pamphlet A13326EJ2V0PF MA-9 Family MA-9 Family Application Examples Analog Front End for PC Peripherals (Printer, Tablet) Pseudo sine wave External load driving 8-bit D/A converter Control signal Analog signal Logic circuit 8-bit D/A converter Analog signal input Reference power supply 8-bit A/D converter Cell-based IC or CPU core Series regulator (for cell-based IC) VDD Power supply monitor circuit Reset circuit Pamphlet A13326EJ2V0PF 23 MA-9 Family Gyro Sensor/Magnetic Sensor (1/2) (Sensor Signal Amplification + A/D Conversion) Analog circuit Sensor 1 12-bit A/D converter Sensor 2 Sensor 3 Digital circuit CPU 10-bit D/A converter 10-bit D/A converter EEPROMTM 24 Pamphlet A13326EJ2V0PF MA-9 Family Gyro Sensor/Magnetic Sensor (2/2) (Sensor Signal Amplification + A/D Conversion) NIN D/A converter YIN Sensor COMMON Analog circuit (amplification) Logic circuit CPU A/D converter Control signal NIN RX YIN COMMON Amplification/gain adjustment Pamphlet A13326EJ2V0PF 25 MA-9 Family Chip Configuration Logic circuit Analog-logic I/F test circuit Test circuit CB-9VX analog IP core Analog circuit Logic circuit User logic (logic gates) A/D or D/A converter macro (CB-9 Family VX Type)Note Test circuit Test circuit including analog-logic I/F block Note Neither a CPU nor ROM can be mounted. Analog circuit Configured by operational amplifier, comparator, reference power supply, analog switch, etc. NEC Electronics designs the circuit according to the user's circuit specifications. 26 Pamphlet A13326EJ2V0PF MA-9 Family Basic Specifications Logic Circuit Part number Process Supply voltage Maximum integration (logic only) Interface level Internal gatesNote 1 Delay time Input bufferNote 2 Output bufferNote 3 PD681 0.35 m BiCMOS process 3.3 V 0.3 V (I/O block, internal gates) 1.7 million gates (usable) LVTTL 114 ps (TYP.) 169 ps (TYP.) 864 ps (TYP.) Notes 1. Value assuming 2-input NAND power gate, fan-out 2, and standard wiring length. 2. Value assuming fan-out 2 and standard wiring length. 3. Value assuming load capacitance 15 pF, IOL = 18 mA. Remark The logic circuit characteristics are the same as those of NEC Electronics' CB-9 Family. Analog Circuit PD681 0.35 m BiCMOS process 3.3 V 0.3 V fT = 10 GHz, hFE = 70 (all TYP.) fT = 2 GHz, hFE = 30 (all TYP.) N-ch type, P-ch type for analog circuit Absolute precision: 20%, relative precision: 2% Absolute precision: 20%, relative precision: 2% Part number Process Supply voltage NPN type Transistors PNP type (vertical type) MOS Polysilicon resistorNote Capacitor (MIM type)Note Note Values indicated are for reference only. The relative precision applies only to when the element is positioned in an adjacent location. Pamphlet A13326EJ2V0PF 27 MA-9 Family Number of Steps and Usable Gates Number of Usable Gates Step Number 2-Layer Wiring B60 C02 C40 C78 D01 D26 D52 D90 E16 E54 E80 F18 F44 F70 G08 G34 G72 H10 H49 H87 J26 J51 K15 K92 89,600 117,700 142,000 176,100 195,700 215,900 242,200 277,900 308,300 344,200 373,300 412,800 448,300 479,800 521,600 554,300 612,600 655,600 714,700 775,400 813,300 855,900 968,800 1,071,600 VX Type 3-Layer Wiring 131,800 174,200 211,500 264,200 293,600 326,200 365,900 422,900 469,200 535,400 572,400 647,300 703,000 741,500 824,900 876,600 954,500 1,045,900 1,140,200 1,218,600 1,309,300 1,377,800 1,536,000 1,741,400 Remark The number of usable gates is calculated using 2-input NAND gate conversion. Moreover, the above-indicated number of usable gates depends on the megafunctions that are provided and the logic use efficiency, and should therefore be treated as a reference value. Remark The number of steps and number of usable gates given for the MA-9 Family indicate the size of the entire internal logic including the mixed signal core. Logic circuit Analog-logic I/F test circuit Test circuit = Number of steps (number of usable gates) CB-9VX analog IP core Analog circuit 28 Pamphlet A13326EJ2V0PF MA-9 Family Electrical Specifications Number of Steps and Usable Gates Absolute Maximum Ratings Item Supply voltage 3.3 V I/O voltage LVTTL buffer Output current IO VI/VO VI/VO < VDD + 0.5 V IOL = 1 mA IOL = 2 mA IOL = 3 mA IOL = 6 mA IOL = 9 mA IOL = 12 mA IOL = 18 mA IOL = 24 mA Operating ambient temperature Storage temperature TA Tstg -0.5 to +4.6 3 7 10 20 30 40 60 75 -40 to +85 -65 to +150 V mA mA mA mA mA mA mA mA C C Symbol VDD -0.5 to +4.6 V Conditions Rating Unit Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Definition of absolute maximum rating terms Item Supply voltage Input voltage Output voltage Input current Output current Symbol VDD VI VO II IO Meaning The range of voltage that, if applied to the VDD pin, will not cause destruction or lower reliability. The range of voltage that, if applied to the input pin, will not cause destruction or lower reliability. The range of voltage that, if applied to the output pin, will not cause destruction or lower reliability. The absolute value of current capacity that, if applied to the input pin, will not cause latchup to occur. The absolute value of DC current capacity that, if output from or input to the output pin, will not cause destruction or lower reliability. Range of ambient temperature in which normal logical operation will occur. Range of pin temperature that will not cause destruction or lower reliability when voltage and current are not applied. Operating ambient TA temperature Storage Tstg temperature Pamphlet A13326EJ2V0PF 29 MA-9 Family Recommended Operating Range Item Supply voltage Negative trigger voltage Positive trigger voltage Hysteresis voltage Low-level input voltage High-level input voltage Input rise time Input fall time Input rise time Input fall time Symbol VDD VN VP VH VIL VIH tri tfi tri tfi Conditions 3.3 V power supply LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer LVTTL buffer Normal input MIN 3.0 0.6 1.2 0.3 0 2.0 0 0 TYP 3.3 MAX 3.6 1.8 2.4 1.5 0.8 VDD 200 200 10 10 Unit V V V V V V ns ns ms ms Schmitt input 0 0 Remark The logic circuit characteristics are the same as those of NEC Electronics' CB-9 Family. 30 Pamphlet A13326EJ2V0PF MA-9 Family Analog IP Core A/D Converter Core Name Power Consumption (MAX.) 18.0 mW 18.0 mW 20.2 mW 504 mW 28.8 mW Differential Linearity Error (MAX.) 1.0LSB 1.0LSB 1.0LSB 1.0LSB 1.0LSB Integral Linearity Error (MAX.) Circuit Type Operating Power Supply Voltage 2.7 to 3.6 V 3.0 to 3.6 V 2.7 to 3.6 V 3.0 to 3.6 V 3.3 V (TYP.) 10 bit-100 kHz-1ch 10 bit-100 kHz-8ch_Mpx 12 bit-300 kHz-4ch_Mpx 6 bit-70 MHz 8 bit-200 kHz-1ch 8 bit-200 kHz-8ch 8 bit-50 MHz 8 bit-8 MHz Remark TA = -40 to +85C 1.5LSB 1.5LSB 4.0LSB 2.0LSB 2.0LSB Successive approximation Successive approximation Successive approximation Flash Successive approximation 108 mW 1.0LSB (TYP.) 1.0LSB (TYP.) Sub-ranging 3.0 to 3.6 V D/A Converter Core Name Power Consumption (MAX.) 3.6 mW 374 mW 90 mW 180 mW 266.4 mW 7.2 mW 90 mW 180 mW T.B.D. Differential Linearity Error (MAX.) 1.0LSB 1.0LSB 0.5LSB 0.5LSB 0.5LSB 1.0LSB 0.5LSB 0.5LSB 1.0LSB Integral Linearity Error (MAX.) 1.0LSB 1.5LSB 2.25LSB 2.25LSB 2.25LSB 1.0LSB 1.0LSB 1.0LSB 3.0LSB Circuit Type Operating Power Supply Voltage 3.3 V (TYP.) 3.0 to 3.6 V 3.0 to 3.6 V 3.0 to 3.6 V 3.0 to 3.6 V 3.3 V (TYP.) 3.0 to 3.6 V 3.0 to 3.6 V Under development (VO = 0.75 V) Remark TA = -40 to +85C 10 bit-100 kHz-1ch 10 bit-135 kHz-1ch 10 bit-30 MHz-1ch 10 bit-30 MHz-2ch 10 bit-30 MHz-3ch 8 bit-200 kHz-1ch 8 bit-30 MHz-1ch 8 bit-30 MHz-2ch 8 bit-30 MHz-3ch Resistor string Resistor string Resistor string Resistor string Resistor string Resistor string Resistor string Resistor string Resistor string Pamphlet A13326EJ2V0PF 31 MA-9 Family MA-9 Family Development Procedure The MA-9 Family is developed by separating the logic circuit and analog circuit and combining the circuit diagram level interface and simulation level interface. Development Method System Circuit Design LSI Circuit Design Circuit Synthesis Layout Design ES Production [logic circuit] Simulation level interface (User side) (NEC Electronics side) [Analog circuit] Circuit diagram level interface 32 Pamphlet A13326EJ2V0PF MA-9 Family Logic circuit: Simulation level interface Analog circuit: Circuit diagram level interface NEC Electronics Development support User Determination of desired system specifications Analog circuit interface System circuit design Circuit specification adjustment Analog circuit: Circuit design, simulation Simulation result verification Confirmation of provisional specifications Confirmation Analog circuit: Placement and routing, core configuration Analog circuit: Test pattern preparation Logic circuit: Logic design, simulation Logic circuit: Floor plan, placement and routing Preparation of test patterns Mask production, ES production ES evaluation Confirmation Test and preparation of product ratings Test and verification of product ratings Confirmation CS production CS evaluation MP production Delivery Pamphlet A13326EJ2V0PF 33 MA-9 Family MA-9 Family Development Tools The MA-9 Family provides development tools that support ASIC development by the user for each logic circuit and analog circuit separately. For the logic circuits, a simple design environment is enabled by using OPENCAD, NEC Electronics' original CAE tool, and for the analog circuits, the design environment is enabled by using a CAE tool ideal for digital-analog integrated circuits. Designed by OPENCAD (NEC Electronics' original CAE tool) Logic circuit Designed by Analog ArtistTM (CAE tool of Cadence Design Systems) Analog-logic I/F test circuit Test circuit CB-9VX analog IP core Analog circuit Analog Artist Circuit diagram entry: ComposerTM Simulator: Spectre/VerilogTMHDL Layout editor: DLE,Virtuoso Layout tester: Diva 34 Pamphlet A13326EJ2V0PF MA-9 Family Design Flowchart OPENCAD System 1 System 2 Logic synthesis Entire circuit netlist LogicSim. Floor plan, layout, etc. Layout data Mixed signal core ADC core Circuit diagram entry Test patterns Logic circuit Analog Artist Mixed signal core test program Test design A/D mix simulator Mixed signal core Layout design and testing Analog circuit Netlist Layout data Analog array design Analog array cell placement and routing Analog array Element layout data Pamphlet A13326EJ2V0PF 35 Packages MA-8A The MA-8A supports various packages, enabling users to select the package type and optimum number of pins for their system and circuit scale (chip size). Mold Packages Package SOP SSOP No. of Pins 20 16 20 20 24 30 36 38 42 48 Lead Pitch (mm) 1.27 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.65 0.8 0.8 0.5 0.65 0.65 1.00 0.5 0.8 1.0 0.65 0.5 1.0 0.5 0.65 0.8 0.4 0.5 0.5 0.65 0.4 0.5 0.5 0.5 0.4 0.5 0.5 Nominal Size 7.62 mm (300) 5.72 mm (225) 5.72 mm (225) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 7.62 mm (300) 9.53 mm (375) 9.53 mm (375) - - - - - - - - - - - - - - - - - - - - - - - - - - Body Size (mm) - - - - - - - - - - 10 10 10 10 77 10 10 10 10 14 14 10 10 14 14 14 20 10 14 10 10 20 20 12 12 14 14 14 20 12 12 14 14 14 14 14 20 14 14 20 20 20 20 24 24 20 20 28 28 32 32 Main Unit Thickness (mm) - - - - - - - - - - 2.70 1.40 1.00 2.20 1.40 2.55 1.00 1.40 2.00 2.20 2.20 3.70 1.00 2.00 2.70 1.00 1.40 1.00 2.20 1.00 2.70 1.40 1.40 1.40 1.40 1.40 QFP 44 44 48 48 52 52 64 64 64 68 72 74 80 80 80 100 100 100 100 120 120 144 160 176 208 240 36 Pamphlet A13326EJ2V0PF Packages CSP (Chip Size Package) Package No. of Pins Ball Array Body Size Production (mm) FPBGA 61 80 161 209 225 249 257 273 303 393 Note 3 4 4 4 4 4 4 4 4 4-0-2 66 77 10 10 12 12 13 13 13 13 14 14 15 15 16 16 16 16 Note Note Note Package No. of Pins Ball Array Body Size Production (mm) Status Status FPLGA 64 84 100 108 112 168 192 224 304 405 3 4 Full Full 4 4 4 4 4 4-0-2 66 7.5 7.5 87 7.5 7.5 88 11 11 11 11 13 13 16 16 16 16 Note Note Under development FPBGA: Fine Pitch Ball Grid Array, FPLGA: Fine Pitch Land Grid Array : Can be produced Blank: In planning Development costs, including the board and sorting jig, will be charged for a CSP. Remarks 1. 2. 3 Pamphlet A13326EJ2V0PF 37 Packages MA-9 Family The MA-9 Family supports various packages, enabling users to select the package type and optimum number of pins for their system and circuit scale (chip size). For packages other than QFP, contact NEC Electronics. Package Type No. of Pins QFP (FP) 100 120 144 160Note 176 208 240 Note Note Note Step Size Lead Pitch (mm) 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 Resin Thickness (mm) 1.45 2.70 2.70 2.70 2.70 3.20 3.20 3.20 1.00 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - B60 C02 C40 C78 D01 D26 D52 D90 E16 External Dimensions (mm) 14 14 20 20 20 20 20 20 24 24 28 28 32 32 40 40 14 14 304Note TQFP Note Remark 100 Low-thermal-resistance type : Can be used, : Under development, -: Cannot be used, Blank: Under study Package Type No. of Pins QFP (FP) 100 120 144 160 176 Note Note Step Size Lead Pitch (mm) 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 Resin Thickness (mm) 1.45 2.70 2.70 2.70 2.70 3.20 3.20 3.20 1.00 - - - - E54 E80 F18 F44 F70 G08 G34 G72 External Dimensions (mm) 14 14 20 20 20 20 20 20 24 24 28 28 32 32 40 40 14 14 - - - 208Note 240 304 TQFP Note Remark Note Note 100 Low-thermal-resistance type : Can be used, : Under development, -: Cannot be used, Blank: Under study 38 Pamphlet A13326EJ2V0PF Packages Package Type No. of Pins QFP (FP) 100 120 144 160 176 Note Note Step Size Lead Pitch (mm) 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 Resin Thickness (mm) 1.45 2.70 2.70 2.70 2.70 3.20 3.20 3.20 1.00 - - - - - - - H10 H49 H87 J26 J51 K15 K92 External Dimensions (mm) 14 14 20 20 20 20 20 20 24 24 28 28 32 32 40 40 14 14 - - - - - - - - - - - - - - - 208Note 240 304 TQFP Note Remark Note Note 100 Low-thermal-resistance type : Can be used, : Under development, -: Cannot be used, Blank: Under study Pamphlet A13326EJ2V0PF 39 40 Pamphlet A13326EJ2V0PF Pamphlet A13326EJ2V0PF 41 42 Pamphlet A13326EJ2V0PF EEPROM, FPBGA, and OPENCAD are trademarks of NEC Electronics Corporation. Analog Artist, Composer, and Verilog are trademarks of Cadence Design Systems, Inc. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of May, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics's willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11 Pamphlet A13326EJ2V0PF 43 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [North America] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.necelam.com/ [Europe] NEC Electronics (Europe) GmbH Oberrather Str. 4 40472 Dusseldorf, Germany Tel: 0211-6503-01 http://www.ee.nec.de/ Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Succursale Francaise 9, rue Paul Dautier, B.P. 52 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven The Netherlands Tel: 040-2445845 Tyskland Filial P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 [Asia & Oceania] NEC Electronics Hong Kong Limited 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. 7th Floor, HSBC Tower, 101Yin Cheng East Road, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 G03.4 Document No. A13326EJ2V0PF00 (2nd edition) Date Published June 2003 N CP(K) (c) NEC Electronics Corporation 1998 |
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